纳米尺度新型半导体存储器件研究

编辑:指甲网互动百科 时间:2020-02-26 08:24:20
编辑 锁定
半导体存储器主要包括挥发性存储和非挥发性存储两大类。随着消费类,便携式电子市场的发展,对半导体存储器的需求越来越大。在市场的驱动下,半导体存储器通过缩小单元尺寸提高存储容量,降低单元成本,等比例缩小已成为半导体存储技术发展的主要驱动力。
中文名
纳米尺度新型半导体存储器件研究
举    例
发性存储和非挥发性存储
技    术
半导体存储技术
分    类
科技存储项目

纳米尺度新型半导体存储器件研究中文介绍

编辑
半导体存储器主要包括挥发性存储和非挥发性存储两大类。随着消费类,便携式电子市场的发展,对半导体存储器的需求越来越大。在市场的驱动下,半导体存储器通过缩小单元尺寸提高存储容量,降低单元成本,等比例缩小已成为半导体存储技术发展的主要驱动力。然而随着存储器件尺寸缩小到纳米尺度,主要的半导体存储器面临诸多严峻挑战,如工艺复杂性提高、短沟特性退化、可靠性下降等。本论文面向动态随机存储器(DRAM)和闪存(Flash memory)两类重要的半导体存储技术,从提高存储密度、提升性能、增强可靠性和降低功耗的角度,围绕器件结构、阵列架构、工艺制备及相关特性分析等方面展开研究。 [1] 
对于DRAM,由于1T1C DRAM在单元尺寸缩小时工艺复杂性增加和单元可靠性下降,嵌入式应用受到了限制。面向嵌入式DRAM应用,通过分析无电容浮体DRAM单元在单元尺寸缩小时性能退化的物理机制,提出了源漏能带工程的浮体DRAM(BESD-FBDRAM)单元结构,并给出了可行的工艺实现方式。新结构浮体单元可以有效减小空穴泄漏,改善单元的存储特性。分析表明, BESD-FBDRAM单元在编程和擦除速度不受影响的情况下,相比传统结构电流窗口可增加3倍左右,保持时间增长10倍以上,并且在小尺寸下电流窗口优势更加明显,具有更好的等比例缩小能力。针对基于双极机理的浮体DRAM单元工作电压高和相应的可靠性问题,提出双极BESD-FBDRAM单元,其保持了有效存储空穴的优势,研究表明,这种结构可以增大双极单元的栅控制窗口,降低工作漏电压,提高单元可靠性。此外,针对阵列应用,提出了源漏非覆盖结构的双极浮体DRAM,以改善单元的抗干扰能力。
  进一步,提出了基于体硅衬底的准SOI结构浮体DRAM单元,可在体硅衬底上制备,更适于嵌入式应用。与基于体硅衬底的传统浮体DRAM单元相比,该新结构可以改善电流窗口和信号保持时间,此外,阵列中的单元可用共源共漏设计,单元面积从10F²缩小到6F²。在面向低功耗应用时,分析了带带隧穿编程方式在准SOI结构浮体DRAM单元的应用,结果表明相比于沟道热电子机制,编程功耗可下降几个数量级,同时电流窗口和保持时间基本相同。
  对于非挥发性的闪存,分别针对快速读取的NOR型闪存和高存储密度的NAND闪存进行了相关研究。对于NOR型闪存,采用双掺杂浮栅闪存(DDFG, Dual Dopoing Floating Gate)结构,开发了基于标准Foundry工艺的小尺寸DDFG闪存工艺。该结构可以提高热电子编程的注入效率,降低编程功耗,提高单元保持特性。通过分析标准工艺小尺寸DDFG闪存工艺制备与大尺寸相比的一些特点,成功制备标准工艺下小尺寸DDFG闪存。实验结果表明,小尺寸DDFG闪存仍具有编程效率提高、功耗下降的特性,而对小尺寸的工艺方案相较于大尺寸设计可靠性也得到了改善。通过测试分析,对工艺进一步优化,提出了一种大马士革工艺方案。
  针对提高闪存存储密度及降低单元成本的要求,提出了一种三维围栅薄膜晶体管(TFT,thin-film-transistor)NAND型闪存及其阵列架构,并设计开发了其工艺制备方案。所提出的三维结构工艺较为简单,各层的主要工艺步骤可以同步完成,可以提高存储密度,减小单元成本;闪存单元采用围栅结构,可以提高TFT闪存的开关性能。通过工艺设计和对关键工艺步骤和参数优化,实验制备出了三维围栅TFT闪存单元及其NAND阵列结构,并测试了单元的开关、存储特性和可靠性。测试结果表明围栅TFT闪存相比于平面结构在电流开关比、亚阈斜率、迁移率、编程和擦除速度等方面都获得较大改善,其中开关电流比达到1×10⁶,迁移率为平面结构20~30倍,单元导通电流达到了对体硅NAND闪存的要求。对三维围栅TFT闪存单元的存储特性的测试和分析表明在一定编程擦除条件,实现的围栅TFT闪存单元具有较高的阈值窗口和可靠性。最后,设计了多级存储的编程擦除条件,进一步论证了三维多级(MLC)NAND的存储特性及可靠性。
  关键词 无电容式DRAM,源漏能带工程,浮栅闪存,薄膜晶体管闪存,三维闪存

纳米尺度新型半导体存储器件研究英语介绍

编辑
With the development of the consumer and portable electronics market, the demands for higher density semiconductor memory are growing fast. In the past few decades, continued device scaling has become the driving force for semiconductor memory development, which dramatically increases memory density and reduces unit cost. However, with the device size shrinking into nano-scaled regime, semiconductor memory faces several challenges, including process complexity, short-channel effect, and reliab...>> 详细
With the development of the consumer and portable electronics market, the demands for higher density semiconductor memory are growing fast. In the past few decades, continued device scaling has become the driving force for semiconductor memory development, which dramatically increases memory density and reduces unit cost. However, with the device size shrinking into nano-scaled regime, semiconductor memory faces several challenges, including process complexity, short-channel effect, and reliability degradation etc.. In this thesis, we will focus on the most important two types of semiconductor memory—DRAM and flash memory. Based on novel device structure, novel array architecture and process development, investigation and innovation are carried out to enhance memory storage density, cell performance, reliability and reduce power consumption.
  The complicated capacitor process and reliability issue hinder 1T1C cell for embedded DRAM applications, while capacitor-less floating body DRAM cell (FBC) has attracted much attention. However, with the cell size scaling down, the performance of FBC is decreased, so a novel band-gap engineered source/drain floating body DRAM (BESD-FBDRAM) cell is proposed. The energy band offset with silicon - carbon source and drain can help to form a deeper potential well in the body region, which can effectively store more holes. Compared with normal FBC, BESD-FBDRAM can obtain 3 times larger signal window and 10 times longer retention time, while write speed keeps the same. In addition, BESD-FBDRAM cell exhibits more significant improvement for shorter channel devices, showing great potentials for further scaled generations. For bipolar FBC, a bipolar BESD-FBDRAM cell is proposed to increase the gate control window, reduce the drain voltage, and thus improve the cell reliability. Furthermore, for array applications, a source and drain underlap structure is also proposed to relieve the drain disturb of bipolar FBC.
  To extend application fields of floating-body DRAM cell, a quasi-SOI structure floating-body DRAM based on bulk silicon substrate is proposed, which is more suitable for embedded DRAM applications. Compared with the bulk substrate floating-body DRAM cell, the quasi-SOI cell can achieve larger current window and longer retention time. Besides, the deep L-shape isolation enables common source/drain design for the adjacent quasi-SOI cell, and thus cell size is reduced from 10F² in normal cell to 6F². Moreover, a band-to-band tunneling programming method for low power consumption is also studied for quasi-SOI floating-body DRAM cell. The results show that compared to CHE (channel-hot-electron) programming method, the power consumption can be decreased by several orders of magnitude while the current window and hold time is almost the same.
  Another issue is flash memory. For NOR flash memory, using a DDFG (Dual Doping Floating Gate) structure, we developed small size DDFG Flash memory process based on standard Foundry process. Due to an electron valley formed in the floating gate, this structure can improve flash cell retention characteristics. Through analysis of different features of DDFG flash memory based on standard Foundry process, we successfully fabricated 0.13um DDFG flash memory. The experimental results show that the small DDFG flash device can improve the programming efficiency and reduce power consumption. Moreover, a damascene process method was proposed to further optimize the DDFG device.
  To continue enhance flash memory density, a three-dimensional gate-all-around (GAA) TFT NAND flash memory and its array architecture are proposed. The process flow of the proposed three-dimensional flash is relatively simple, as the memory cells of each layer can be formed synchronically, which can increase the storage density and reduce bit-cost. Then by process design and optimization, the three-dimensional TFT flash memory is demonstrated experimentally. Compared with the planar TFT flash cell, the GAA cell exhibited improved sub-threshold slope, carrier mobility and writing speed, which can overcome the difficulties for TFT applied to NAND flash memory. The measurement results show that the GAA TFT flash memory has a large memory window and good reliability characteristics. Finally, multi-level per cell (MLC) program/erase schemes are proposed and 3D MLC NAND flash is further demonstrated.
  Key Words: floating body cell, band-gap engineered source/drain, floating gate flash, thin-film-transistor flash, three-dimensional flash
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